Solid state semiconductor devices consume power within its operational circuitry when operating, and also when they are in an idle or stand-by state. Many applications of such semiconductor devices, for example mobile and biomedical applications, operate stand-alone or without readily available power, so it is desirable to minimize such power consumption.
This is particularly true for integrated circuits which contain significant amounts of memory. A semiconductor memory subsystem can be divided into two regions: One region is an array of storage cells, typically organized as a two-dimensional array of memory bit cells, where individual cells are accessible using addressable cell access lines or busses. The other region is an arrangement of logic devices, whose purpose may include supporting the cell array. For instance, many System on Chip (SoC) devices contain large arrays of such memory cells. The memory subsystem constitutes a major part (typically up to 70%) of the silicon area for a typical SoC device.
In a memory device having an array of cells, the device consumes power for each cell. Therefore, due to factors of heat generation and dissipation, and efficiency of operation, power consumption is a noteworthy design consideration.